This invention relates to semiconductor electronic integrated circuits (chips) of the type comprising configurable logic circuit arrays, and systems utilising them.
Two types of such circuits are available at present. One type is the so-called uncommitted logic array (ULA) in which a chip is first made with unconnected logic gates, i.e. each isolated at its own site on the chip, and interconnection for particular purposes is achieved by means of a specially configured metallisation layer applied later. Usually, the gate sites are substantially uniformly distributed over the usable area of the chip or at least a central part of such area. Currently, ULAs are available with from 500 to 5000 gates available and will doubtless increase in gate capacity as technology develops. Typically, around 60%-80% of available gates are utilised after interconnection to configure a ULA for a particular purpose, it being in the nature of electronic circuit/system design that various local configurations of interconnected gates perform particular functions and are further interconnected for overall circuit/system requirements, leaving some gates unused. Designing masks for such customised metallisation layers is time-consuming and expensive. Also, it is highly intolerant of errors as remasking is necessary whenever prototypes malfunction by reason of design fault.
The other type is the so-called programmable gate array (PGA) in which a chip is formed with logic gates of which all or most are each individually interconnected with all or most of the others in most if not all conceivable ways. The PGA as made is configured by fusing out unwanted ones of the interconnections. Usually, the gates are formed at edges of the usable area of the chip or that part dedicated to PGA gate purposes, and a more central part of such area is occupied by a grid of interconnections fusible at crossing points or connecting devices. Not surprisingly, gate capacities are very much lower than for ULA's, often effectively about 50 gates or less in terms of inclusion in actual logic functions. The capability of PGA's in terms of putting complex electronic circuit/systems into integrated circuit form is correspondingly limited compared with ULA's. However, PGA's do have a very considerable advantage to the circuit designer, who need only take up another chip and start again whenever an error is made or malfunction is encountered requiring re-design.
It would manifestly be of great advantage and practical utility to have configurable integrated circuits with greater gate capacity than such PGA's (say at least an order of magnitude greater if not approaching the gate capacities of ULAs), but retain the ease of designer-use and freedom from masking-up costs that characterise PGAs compared with ULAs. It is towards providing such semiconductor integrated circuits that this invention first directs its attention.
Several aspects of this invention arise in relation to the teaching hereof, and one aspect can be viewed as starting from questioning the hitherto-accepted practice in relation to PGAs for all gate interconnection possibilities to be provided as-made and before configuration.
According to that aspect of this invention, a configurable semiconductor integrated circuit (chip) as-made has formed therein a plurality of logic circuits at discrete sites and a restricted signal translation system between inputs and outputs of said logic circuits affording direct connection paths between each of said logic circuits and only a few others of said logic circuits, which connection paths are selectable as to their conduction state. Indirect connections to further of said logic circuits are available through one or more others of said other logic circuits.
Suitable said selectable connection paths extend, for each logic circuit, from output thereof to inputs of a first set of others of said logic circuits, and to inputs thereof from outputs of a second set of others of said logic circuits, all of the sets (for all of the logic circuits) each being unique. Normally, first and second sets associated with a particular logic circuit will have at least one said other logic circuit in common and most often at least one each not in common. Generally, each set will usually be a small proportion, less than 5%, of the total number of logic circuits. It is envisaged that in many embodiments the number of logic circuits in a set will be 10 or less. Conveniently, the number in a set may be as small as five, but at least three except at edges of an array.
The term "as-made" as used herein means the chip (or some part thereof) in the state in which it is manufactured and prior to any operation to effect configuration. The term "selectable" as used herein in relation to a connection path comprehends that the condition of the path as to whether or not it conducts in order to transmit electrical signals can be determined relative to its as-made condition by application of appropriate selection signals or signal conditions. The term "logic circuit" as used herein is not intended to be restricted to the single function logic gates (such as NAND) used in illustrated embodiments, in fact could cover any logic circuit whose use with interconnect provisions hereof proves to be feasible.
The direct connection paths are normally between physically neighbouring logic circuit sites, which, whilst not essential, facilitates establishment of a desired particular circuit function in a localised configuration of logic circuits, i.e. in part only of the chip area occupied by an appropriate number of discrete sites of the logic circuits and by the direct connection paths. Interconnections between such localised configurations for overall circuit/system requirements can be either simply by said direct connection paths or by said indirect connections through selected ones of the logic circuits. The inclusion of one or more logic circuit transit times in some actual configured indirect connections is usually of small significance as such need not exceed about 3 nanoseconds on present-day technology, at least for simple logic gate circuits.
We shall describe conduction selection provisions for the direct connection paths at inputs to the logic circuit sites, i.e. in relation to said second set of paths as entering the site. However, they could equally well be provided elsewhere, for example at logic circuit outputs, particularly in branches therefrom (i.e. in relation to said first set of paths as leaving the site), or at combinations of inputs and outputs of logic circuit sites.
Concerning said direct connection paths and appropriate physical dispositions of logic circuit sites on a chip, it is convenient to consider matters in logic diagram terms correlating each logic circuit site as viewed on the surface of a chip of semiconductor material with a logic circuit symbol. The symbols/sites will usually be arranged in an overall disposition of discernable regularity or pattern with spaces between those logic circuit symbols/sites carrying said direct connection paths. Examples of such regularity or pattern are matrix arrays though there may well be offsets or staggers of logic circuit sites in and/or between rows and/or columns. Such logic circuits may "point" in different directions reflected on the area of the chip as sites being oppositely formed in terms of access to inputs and outputs (or considering their outputs as establishing a direction after the manner of an arrow-head). Several alternative dispositions of logic circuits, and their sites are indicated with reference to the drawings, and others may be equally or more efficient or effective, at least in particular circumstances.
A presently preferred disposition in a basic row-and-column, matrix-like, array, has each of its logic circuits in each row "pointing" in one direction and connected by a selectable connection path from its output to input of the next following logic circuit in the row. Further preferably, such directions of successive rows alternate thus making overall zig-zag or snake-like indirect paths available throughout. Further preferably, such logic circuit outputs are selectably connected to inputs of the next adjacent logic circuits in the same columns, i.e. those in the next adjacent rows. That makes available paths running along columns, respectively. Overall, such a disposition gives flexibility of selectable direct connections between neighbouring logic circuits in a compact overall arrangement of logic circuit sites. Such flexibility of interconnection is extendable in a particularly advantageous way by a further selectable direct connection path from output of each logic circuit to input of the next-but-one logic circuit in the same row going in the same direction as the direct connection to the next logic circuit.
The words "row" and "column" will usually have some perceptible reflection in actual dispositions of logic circuit sites on a chip but are used herein mainly for ease of explanation, i.e. not for necessarily implying exactitude of logic circuit site lay-out/topography. It should, however, be clear that all embodiments of this invention are intended to permit selection of connection paths for configuration purposes relative to logic circuit site dispositions that can be substantially uniformly disposed over at least part of the relevant area of a chip.
There is another aspect of this invention concerning selectable connection provisions traversing chip area of prime capability for formation of logic circuit sites.
According to that aspect a configurable semiconductor integrated circuit (chip) as-made has a plurality of logic circuits formed therein distributed over at least part of its usable area, and a direct signal translation provision comprising at least one conducting path associated with selectable connection paths for inputs and outputs of said plurality of logic circuits or at least one subset thereof. Such path or paths can be wholly or mainly in and along spaces between discrete sites of said logic circuits with selectable branch paths into those sites. This provision is called herein a direct connect bus system whose paths traverse more of the logic gate sites than can be reached by the first-discussed direct connection paths.
Whilst obviously applicable alone, this aspect has particular advantage when employed in conjuction with the direct connection paths of said restricted signal translation system in order to provide selectable other direct connections between non-neighbouring logic circuit sites. Such provision avoids logic circuit transit times of said indirect connections and allows direct connections between groups of sites in different regions of said area. Dedicated such other conducting paths can extend along rows and columns of a matrix array of logic circuits. Branches to two dedicated inputs at each logic circuit site can then be selectable, as can further preferred branches from each logic circuit output. Connections by way of such direct connect bus connection paths can go along selected rows or columns and from one to another thereof in any desired way, including providing disconnected segments. It is not necessary for the conducting paths of such a direct connect bus system all to be metallised as at least parts may be paths through host semiconductor material of enhanced conductivity, for example polysilicon for silicon host material. Also, neither direction of row and column conducting paths need extend continuously over the whole array of logic circuit sites. They can be confined to a subset of the logic gates of the array, or be provided localised to each of several subsets. Any necessary further interconnection relative to the subsets can be through a logic circuit or circuits.
It can be advantageous for segmented sections of such paths, which may correspond to different subsets, to overlap each other by at least one logic circuit site. Segmented provisions are particularly useful for conductivity-enhanced paths or parts of paths as they should then be of limited extent, say up to six logic circuit sites, in view of their greater impedance compared with metallised paths. For example, the row-following paths could be metallised, perhaps interrupted once with possible interconnection through a logic circuit, whilst the column-following paths could be of polysilicon in much shorter interleaved and overlapped lengths and also interconnectable by means of logic circuits.
It is found convenient for all selection provisions of input connection paths to a particular logic circuit, and any selection provisions of output connection paths therefrom, to be adjacent to that particular logic circuit, and thus be considered as included in the logic circuit site.
To provide for selective addressing of logic circuit sites, (in relation to configuring selectable connection paths to their inputs or from their outputs), spaces between them can be further traversed by specific row and column extending conducting paths (address paths). The latter conveniently enter the site of each logic circuit through branches from each of corresponding row and column address paths, and have associated further circuitry to serve in affording (by coincident energisation) circuit conditions contributing to selection of required selectable connection paths, for example establishing voltage levels assuring required response to an actual configuring signal.
For configuring addressed logic circuits in relation to their selectable and desired connection paths, it is further an aspect hereof that a configuring (program) bus system is provided having a number of (program) conducting paths corresponding to the maximum number of selectable connection paths in any of the logic circuit sites. The program conducting paths traverse (usually between but branched into) all of the logic circuit sites and operate at least to complete circuit conditions required for configuration, usually to deliver configuring electrical signals.
Then, the address paths can condition all of the selectable paths at logic circuit sites as selected sequentially, and, at each site in turn, the program paths cooperate to effect the required configuration by changing the conduction state of appropriate selectable connection paths. For the purposes of selectability, circuit elements are provided, one per selectable connection path, and the as-made conduction state of those circuit elements can be changed by a said configuring electrical signal or circuit condition.
An alternative is for more address paths to go to each logic circuit site and to have coded connections relative to the selectable connection paths at that site so as sequentially to achieve at least conditioning of a different one or more (less than all) of the selectable connection paths.
That leads to provision of two or more of each of row and column address paths, but to a reduction in the number of program paths required. Each of the reduced number of program paths will service more than one of the selectable connection paths at each logic circuit site but only one of them will be conditioned at any one time by the address paths. Where there are enough address paths to identify each selectable connection path at each site, the program paths could be replaced by a single configuring signal path, otherwise enabling of address path energisation could be on a selective basis if such energisation is enough also to achieve circuit conditions causing configuration automatically.
At least where the circuit elements of the selectable connection paths are normally conducting in the chip as-made, and to be rendered irreversibly non-conducting, they can comprise what we call conducting links, whether of fusible conductor or of other disablable type (say a diode to be "blown"). Associated further circuitry will normally include an active circuit device conditioned to pass a disabling electric current as a said configuring signal. Otherwise, blocking signals might be used for controlling current steering means (of said further circuitry) by which disabling current flow will otherwise be applied to each of those circuit elements of the addressed logic circuit site whose steering means is not blocked.
An alternative to fusible or otherwise irreversibly disabled conducting links comprises switchably conducting/non-conducting circuit elements, typically active circuit components, for example transistors. Then, signals on the address and program paths, or coded address paths only, can be used to provide suitable conditions for setting the reversible conduction state of those circuit elements. Typically, active circuit devices (for example also transistors) of associated further circuitry are in suitable circuit configuration with the selectably conducting/non-conducting circuit elements to condition the latter for conduction. Some embodiments of this invention will have configured conduction states that, in operation, remain until reconfigured (static) and other embodiments will require refreshing of their configured conduction states (dynamic).
For CMOS integrated circuit technology, charge-trapping transistors, for example floating gate transistors or oxide-nitride sandwich transistors, can set up selected conduction states that are static for associated selectable connection paths in a manner somewhat analagous to that used in relation to EPROMs. Here, though, such charge-trapping transistors are used to control circuit elements comprising normal MOS transistors, specifically to determine whether those MOS transistors are to be conductive as selectively configured.
An alternative would be to establish such control conditions by way of combinations of MOS transistors and capacitors in a manner analagous to that used in relation to so-called dynamic read/write memories (DRAMS), but then, of course, requiring refreshing, i.e. on a dynamic basis.
A significant development concerning use of single signal-pass field-effect transistors as selectable connection-controlling circuit elements is the subject of another patent application.
Basically, in a field effect semiconductor chip, a single signal-pass transistor is connected between bit signal input and bit signal output and has its control electrode connected for temporary energisations by switching circuitry operative only at prescribed intervals, the single signal-pass transistor being operative to pass signals between such energisations of its control electrode. Those energisations render the single signal-pass transistor conductive, i.e. enabled for conduction, and that conduction is caused to persist, though with some decay, hence periodic refreshing at said prescribed intervals. Inherent capacitance of the single signal- pass transistor inevitable results in accumulation of charge during each said energisation applied to its control electrode. The switching circuitry operates, not to apply discharge voltage between such energisations at said prescribed intervals, but rather to leave the control electrode "floating" between refreshes by said energisations. Such single signal-pass transistors are, of course, capable of continuous signal passage despite only intermittent energisation of their control electrodes.
We further propose an alternative single signal-pass transistor for bipolar semiconductor chips, which will also operate at or near normal logic voltage levels and speeds, and do so without requiring refreshing. That proposal involves circuit formations resembling, at least in action, a silicon-controlled-rectifier (SCR) associated with another transistor for selection to condition for triggering that will force the single signal pass transistor into conduction until reset or loss of power supply. At least for a NAND gate, the signal-pass transistor can effectively be an input stage of the gate.
It should be evident that envisaged alternatives to irreversibly fusible or disabled links or parts, indeed all feasible reversible conduction schemes/devices lead to integrated circuits of this invention that are reconfigurable.
Amongst important implications is the possibility of re-using the same chip, whether by a designer in prototyping or developing a particular system/function, or by a manufacturer to adjust his inventory. Chips employing charge-trapping transistors could be reconfigured by suitable equipment, for example an EPROM writer, whether working from a model or master chip or from the contents of some store that could be part of a programmed computer system serving as a design terminal and/or library of available configurations. Any such applied configuration will be static, i.e. not require refreshing, but configuration will usually be much slower and require much higher signal levels than appies to its subsequent operation as a configured logic system. That would militate against reconfiguration in actual use, though EEPROM chip development may make that feasible.
However, there is the possibility of reconfiguring at or near normal logic signal levels and speeds, which would apply to the afore-mentioned chips using DRAM- type MOS transistor/capacitor combinations, and is yet more efficiently achieved by our single signal pass transistor proposals. Such chips of field effect type are generally of a dynamic nature requiring refreshing of any resident configuration, but bipolar chips can be of a static nature using our SCR-related proposal.